One technique that has been used to protect arbitrary control logic and associated execution data paths is to execute the same instruction stream on two or more processors in parallel. Such processors are said to execute two copies of the instruction stream “in lockstep,” and therefore are referred to as “lockstep processors.” This disclosure relates to a method of synchronizing cross-checked lockstep processors.
A “multi-core” processor may include one or more processor cores on a single chip. A multi-core processor behaves as if it were multiple processors. Each of the multiple processor cores may essentially operate independently, while sharing certain common resources, such as a cache or system interface. In some existing systems, multiple cores within a single microprocessor may operate as lockstep processors.
Generally, two or more lockstep processor cores execute the same instruction for security, backup, and data integrity purposes. However, the processing functions of such lockstep processors typically diverge during the post-reset initialization process because the processor cores are not yet fully synchronized. In order for such initial synchronization to occur, each core must be initialized, such as by executing various routines to force such synchronization.
Once the post-reset initialization process is completed without crosschecking errors, normal post-reset crosschecking—and its associated locking mechanism—may be initiated. However, during the time of incremental synchronization (i.e., before the post-reset locking mechanism can be enabled) it is very difficult to capture the first instance of an error.